INFMT=1_10_BIT, DBGMD=RUN, IDACEN=DISABLED, LOADEN=DISABLED, OUPDT=DACNT8, WRAPEN=DISABLED, JSEL=RIGHT, OUTMD=0P5_MA, TRIGINH=INACTIVE, WEIEN=DISABLED, URIEN=DISABLED, DMARUN=DISABLED, ORIEN=DISABLED, ETRIG=DACNT0
Module Control
| OUPDT | Output Update Trigger. 0 (DACNT8): The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source. 1 (DACNT9): The IDAC output updates using the DACnT9 (Timer 0 High Overflow) trigger source. 2 (DACNT10): The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source. 3 (DACNT11): The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source. 4 (DACNT12): The IDAC output updates on the rising edge of the trigger source selected by ETRIG. 5 (DACNT13): The IDAC output updates on the falling edge of the trigger source selected by ETRIG. 6 (DACNT14): The IDAC output updates on any edge of the trigger source selected by ETRIG. 7 (DACNT15): The IDAC output updates on write to DATA register (On Demand). |
| ETRIG | Edge Trigger Source Select. 0 (DACNT0): Select DACnT0 (DAC0T0 routed through crossbar) as the IDAC external trigger source. 1 (DACNT1): Select DACnT1 (RESERVED) as the IDAC external trigger source. 2 (DACNT2): Select DACnT2 (RESERVED) as the IDAC external trigger source. 3 (DACNT3): Select DACnT3 (RESERVED) as the IDAC external trigger source. 4 (DACNT4): Select DACnT4 (RESERVED) as the IDAC external trigger source. 5 (DACNT5): Select DACnT5 (RESERVED) as the IDAC external trigger source. 6 (DACNT6): Select DACnT6 (RESERVED) as the IDAC external trigger source. 7 (DACNT7): Select DACnT7 (RESERVED) as the IDAC external trigger source. |
| OUTMD | Output Mode. 0 (0P5_MA): The full-scale output current is 0.5 mA. 1 (1_MA): The full-scale output current is 1 mA. 2 (2_MA): The full-scale output current is 2 mA. |
| INFMT | Data Input Format. 0 (1_10_BIT): Writes are interpreted as one 10-bit sample. 1 (2_10_BIT): Writes are interpreted as two 10-bit samples. 2 (4_8_BIT): Writes are interpreted as four 8-bit samples. |
| DMARUN | DMA Run. 0 (DISABLED): Read: No DMA operations are occurring or the DMA is done. Write: No effect. 1 (ENABLED): Read: A DMA operation is currently in progress. Write: Start a DMA operation. |
| JSEL | Data Justification Select. 0 (RIGHT): Data is right-justified. 1 (LEFT): Data is left-justified. |
| BUFRESET | Data Buffer Reset. 1 (RESET): Initiate a data buffer reset. |
| TRIGINH | Trigger Source Inhibit. 0 (INACTIVE): The selected trigger source will cause the IDAC output to update. 1 (ACTIVE): The selected trigger source will not update the IDAC output, except for On-Demand DATA writes. |
| WRAPEN | Wrap Mode Enable. 0 (DISABLED): The IDAC will not wrap when it reaches the end of the data buffer. 1 (ENABLED): The IDAC will cycle through the data buffer contents. |
| ORIEN | FIFO Overrun Interrupt Enable. 0 (DISABLED): Disable the FIFO overrun interrupt (ORI). 1 (ENABLED): Enable the FIFO overrun interrupt (ORI). |
| URIEN | FIFO Underrun Interrupt Enable. 0 (DISABLED): Disable the FIFO underrun interrupt (URI). 1 (ENABLED): Enable the FIFO underrun interrupt (URI). |
| WEIEN | FIFO Went Empty Interrupt Enable. 0 (DISABLED): Disable the FIFO went empty interrupt (WEI). 1 (ENABLED): Enable the FIFO went empty interrupt (WEI). |
| DBGMD | IDAC Debug Mode. 0 (RUN): The IDAC module will continue to operate while the core is halted in debug mode. 1 (HALT): A debug breakpoint will cause the IDAC module to halt (ignore update triggers). |
| LOADEN | Load Resistor Enable. 0 (DISABLED): Disable the internal load resistor. 1 (ENABLED): Enable the internal load resistor. |
| IDACEN | IDAC Enable. 0 (DISABLED): Disable the IDAC. 1 (ENABLED): Enable the IDAC. |